Focus areas include but are not limited to: OS and RTOS porting; early boot; BSPs; MMU/MPU; low-level debug. Prospective team members require strong C/C++; OS/RTOS porting experience; CPU and memory systems knowledge; JTAG/UART debug; RISC-V experience prefered. Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 Read more.

Focus areas include but are not limited to: Build debugging, tracing, profiling, and SDK tools for developers and internal teams. Prospective team members require strong C/C++ skills; Python skills; embedded systems and debug experience; RISC-V experience preferred. Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 Read more.

Focus areas include but are not limited to: Board and SoC bring-up, bootloaders, BSPs, and low-level debug. Prospective team members require strong C/C++; bring-up experience; hardware understanding; JTAG/UART debug; Linux/RTOS; RISC-V experience preferred. Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 days on-site, 1 day Read more.

Focus areas include but are not limited to: RTL and system-level verification, UVM, assertions, coverage, debug. Prospective team members require strong Verilog/SystemVerilog and UVM; RTL debug skills; processor/SoC experience; RISC-V experience preferred. Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 days on-site, 1 day remote. Read more.

Focus areas include but are not limited to: RTL synthesis, STA, timing closure, constraints, sign-off. Prospective team members require strong Verilog/SystemVerilog; STA expertise; SDC; synthesis/STA tools; processor/SoC experience preferred. Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 days on-site, 1 day remote. Policy may change. Read more.

Focus areas include but are not limited to: FPGA-based SoC emulation for pre-silicon validation and software bring-up. Prospective team members require strong Verilog/SystemVerilog; FPGA synthesis/P&R; SoC experience; timing closure; RISC-V experience preferred. Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 days on-site, 1 day remote. Read more.

Focus areas include but are not limited to: Cache, Memory Management Unit (MMU), Multi-Core & Bus Coherence, Branch Prediction, Debug & Test Structures. Prospective team members require experience in at least one focus area; strong Verilog/SystemVerilog skills; RISC-V experience preferred. Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation Read more.