Issuing instructions to multiple execution units Read more.

System and method for a cache in a multi-core processor Read more.

Tool-level and hardware-level code optimization and respective hardware modification Read more.

Optimization of loops and data flow sections in multi-core processor environment Read more.

Providing code sections for matrix of arithmetic logic units in a processor Read more.

Instruction issue to array of arithmetic cells coupled to load/store cells with associated registers as extended register file Read more.

System and method for a cache in a multi-core processor Read more.

Optimization of loops and data flow sections in multi-core processor environment Read more.