Focus areas include but are not limited to: FPGA-based SoC emulation for pre-silicon validation and software bring-up.

Prospective team members require strong Verilog/SystemVerilog; FPGA synthesis/P&R; SoC experience; timing closure; RISC-V experience preferred.

Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role.

Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.