Focus areas include but are not limited to: Cache, Memory Management Unit (MMU), Multi-Core & Bus Coherence, Branch Prediction, Debug & Test Structures.

Prospective team members require experience in at least one focus area; strong Verilog/SystemVerilog skills; RISC-V experience preferred.

Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role.

Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.

We have multiple openings.