We are looking for a Senior Software Engineer who is at home across our processor software from ported libraries and the compiler down to bare-metal and operating systems. Your team will: develop our software stack, including compiler, mapping tools, low-level tooling, simulation and debug infrastructure; write bare-metal, firmware and OS-level software for our RISC-V SoC;… Read more.

Focus areas include but are not limited to: Cache, Memory Management Unit (MMU), Multi-Core & Bus Coherence, Branch Prediction, Debug & Test Structures. Prospective team members require experience in at least one focus area; strong Verilog/SystemVerilog skills; RISC-V experience preferred. Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation… Read more.

Focus areas include but are not limited to: RTL and system-level verification, UVM, assertions, coverage, debug. Prospective team members require strong Verilog/SystemVerilog and UVM; RTL debug skills; processor/SoC experience; RISC-V experience preferred. Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 days on-site, 1 day remote.… Read more.

Focus areas include but are not limited to: synthesis, STA, timing closure, place & route and/or sign-off. Prospective team members require strong Verilog/SystemVerilog; STA expertise; SDC; synthesis/STA tools preferred. Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.… Read more.

We are looking for a Compiler Engineer who will develop new heuristics for a place-and-route tool and take over its overall maintenance and integration. Focus areas include, but are not limited to: Design and implementation of heuristics based on feedback from our application engineers; taking over the ongoing maintenance and improvement of the tool; integration… Read more.